small reorg, split memory into separate module with its own read/write ports
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 22 Apr 2019 02:52:23 +0000 (03:52 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 22 Apr 2019 02:52:23 +0000 (03:52 +0100)
commit0e8cdd821699ce83cf536cf8e8dde72b4557d4e3
tree15a970ff37a770601c06b48629defc900c96b4fd
parente2ef59c86b9dd4940bcc8c28d5b2d4ec61e726d6
small reorg, split memory into separate module with its own read/write ports
TLB/src/SetAssociativeCache.py