git.libre-soc.org Git - litex.git/commit

author	Florent Kermarrec <florent@enjoy-digital.fr>
	Thu, 31 Mar 2016 22:09:17 +0000 (00:09 +0200)
committer	Florent Kermarrec <florent@enjoy-digital.fr>
	Thu, 31 Mar 2016 22:09:17 +0000 (00:09 +0200)
commit	17f6cb1f1740c39039a602e8a95798c50db4c2f6
tree	51723827a6d4470336bb65b0a0125fda3fad743b	tree
parent	7e62cdf6011fd47849a0a4b89ce0d17551b653be	commit \| diff

initial RISC-V support (with picorv32), still some software to do (manage IRQ, L2 cache flush)

14 files changed:

.gitmodules		diff \| blob \| history
MANIFEST.in		diff \| blob \| history
litex/soc/cores/cpu/picorv32/__init__.py	[new file with mode: 0644]	blob
litex/soc/cores/cpu/picorv32/core.py	[new file with mode: 0644]	blob
litex/soc/cores/cpu/picorv32/verilog	[new submodule]	blob
litex/soc/integration/cpu_interface.py		diff \| blob \| history
litex/soc/integration/soc_core.py		diff \| blob \| history
litex/soc/software/bios/boot-helper-riscv32.S	[new file with mode: 0644]	blob
litex/soc/software/bios/sdram.c		diff \| blob \| history
litex/soc/software/include/base/irq.h		diff \| blob \| history
litex/soc/software/libbase/crt0-riscv32.S	[new file with mode: 0644]	blob
litex/soc/software/libbase/system.c		diff \| blob \| history
litex/soc/software/libcompiler_rt/Makefile		diff \| blob \| history
litex/soc/software/libcompiler_rt/mulsi3.c	[new file with mode: 0644]	blob