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(parent: 7db94d6) | patch
bit of a mess. getting carry recognised and output for shiftrot
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 19 Jun 2020 12:45:01 +0000 (13:45 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 19 Jun 2020 12:45:01 +0000 (13:45 +0100)
commit2e85730b3f549508e7aeef8506eff3fa59f012b9
treec00ef0e828eae6766cb37cb2dc8600c0e92d27b5tree
parent7db94d68ed79fc82f0e82ac977e4f35f2e7b1596commit | diff
bit of a mess.  getting carry recognised and output for shiftrot
was interfering with fixedarith carry "implicit" computation.
had to special-case this in pywriter.py and parser.py
src/soc/decoder/isa/caller.py diff | blob | history
src/soc/decoder/power_pseudo.py diff | blob | history
src/soc/decoder/pseudo/parser.py diff | blob | history
src/soc/decoder/pseudo/pywriter.py diff | blob | history