projects / libreriscv.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 434757c) | patch
add page use ulx3s fpga gpio pins for Libre-SOC JTAG connections to STLINKV2
authorcolepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0 <colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0@web>
Sun, 1 Nov 2020 21:38:31 +0000 (21:38 +0000)
committerIkiWiki <ikiwiki.info>
Sun, 1 Nov 2020 21:38:31 +0000 (21:38 +0000)
commit4813678c70cf609bb3fd45d253977dafb9af22c1
tree53bd02697f5b3db8ebfa72bbb965f181ad914870tree
parent434757cc432ee7e02f9f6374ac2242214dcee7b3commit | diff
add page use ulx3s fpga gpio pins for Libre-SOC JTAG connections to STLINKV2
HDL_workflow/fpga.mdwn [new file with mode: 0644] blob
http://libre-riscv.org ikiwiki