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(parent: 3f4ccdf) | patch
synth_gatemate: Revise block RAM read modes and initialization
authorPatrick Urban <patrick.urban@web.de>
Mon, 11 Oct 2021 08:19:29 +0000 (10:19 +0200)
committerMarcelina Kościelnicka <mwk@0x04.net>
Sat, 13 Nov 2021 20:53:25 +0000 (21:53 +0100)
commit4bee908ae87cdff122c21d5f60943731735952fc
treed6417a368b4b19f84273e4fe21b9b69a20e52059tree
parent3f4ccdf2f5c2d8ee54f594914f201630867ea050commit | diff
synth_gatemate: Revise block RAM read modes and initialization

* enable mixed read-width / write-width ports in SDP mode
* fix NO_CHANGE and WRITE_THROUGH behavior during read access
* remove redundant zero-initialization
* set A/B_WE bit during map (gatemate_bramopt pass could be removed later)
* differentiate "upper" and "lower" initialization for cascade mode
techlibs/gatemate/brams_init_40.vh diff | blob | history
techlibs/gatemate/brams_map.v diff | blob | history
techlibs/gatemate/cells_sim.v diff | blob | history