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(parent: 705cbd9) | patch
ha ha very funny. pipelines being pipelines, you have to wait for them
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 9 Jul 2020 19:54:09 +0000 (20:54 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 9 Jul 2020 19:54:09 +0000 (20:54 +0100)
commit4dc4160e6c3545785c32a21fdfd7e30826ee3224
tree513099a87fba317737e1d468d71c87693cc57e60tree
parent705cbd9d1a435281e3a239f20027deda47421b6bcommit | diff
ha ha very funny.  pipelines being pipelines, you have to wait for them
just as with MUL, it was necessary to set the "valid" signal for
only one cycle otherwise spurious output is created
src/soc/fu/div/test/test_pipe_caller.py diff | blob | history