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(parent: ff03c29) | patch
bug #672: invert testing in sv.minmax and add Rc=1
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 8 Dec 2023 15:38:26 +0000 (15:38 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 8 Dec 2023 15:38:26 +0000 (15:38 +0000)
commit585502dba30a0c8cee570f0983b62769b9fb2e8f
treee3ffe7d114e2eeb6c93526fb70d9e120cecc9783tree
parentff03c294d0fc1164e4f56c1736869f9703c7e8f8commit | diff
bug #672: invert testing in sv.minmax and add Rc=1
src/openpower/decoder/isa/test_caller_svp64_dd_ffirst.py diff | blob | history