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(parent: 6c67636) | patch
ha! found source of XICS test bug: wishbone stb was being left HI
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 30 Jul 2020 09:39:43 +0000 (10:39 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 30 Jul 2020 09:39:43 +0000 (10:39 +0100)
commit63eba0f286fb6ea4717db37aa6d5491a4c22700c
treeb036f5b0393037f06af4fc9608257f4d72691880tree
parent6c67636217a5315219217df55ad9f4bae1ce8850commit | diff
ha! found source of XICS test bug: wishbone stb was being left HI
for more than one cycle in the *unit* test, thereby putting spurious
data onto the bus and corrupting transactions
src/soc/interrupts/xics.py diff | blob | history