cores: add simple and minimal hardware SPI Master with CPOL=0, CPHA=0 and build time...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 5 Jul 2019 13:49:17 +0000 (15:49 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 5 Jul 2019 13:50:58 +0000 (15:50 +0200)
commit6b82f23ce191af914b5a0a57feebe6873915aa2a
treeec939e7c8879d95536d2372ffbe46f0c7e9bc8ad
parentada70e8c521a5cea7776005af99fec7f2461e079
cores: add simple and minimal hardware SPI Master with CPOL=0, CPHA=0 and build time configurable data_width and frequency.
litex/soc/cores/spi.py [new file with mode: 0644]
test/test_spi.py [new file with mode: 0644]