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(parent: 92d9582) | patch
add (and ues) PRTBL Record in MMU
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 20 Dec 2021 13:14:12 +0000 (13:14 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 20 Dec 2021 13:14:12 +0000 (13:14 +0000)
commit8bcc7c756ac66c18c858fc3cdfe61257a006f040
treefc3b356c4e995c54f45523cd77e1d42e8175f71etree
parent92d95824dfef321afa066d1602ba5b18f0ce477fcommit | diff
add (and ues) PRTBL Record in MMU
PRTBL: Page Table Record.  it is identical in format and naming PGTBL
src/soc/experiment/mmu.py diff | blob | history