support 32-bit mem width setting
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 23 Jul 2020 21:42:59 +0000 (22:42 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 23 Jul 2020 21:46:06 +0000 (22:46 +0100)
commitc8544d3653c6e49a71eeb6afb2cbdeb3a8bb40c1
tree04eee0935291f2385d846ecec6e79512adbdcca5
parentb72b1ff6810cbcf617217b2fa5095d4a6b92bd69
support 32-bit mem width setting
src/soc/litex/core.py
src/soc/simple/issuer_verilog.py
src/soc/simple/test/test_issuer.py