git.libre-soc.org Git - gcc.git/commit

author	Andrea Corallo <andrea.corallo@arm.com>
	Wed, 21 Oct 2020 09:16:01 +0000 (11:16 +0200)
committer	Andrea Corallo <andrea.corallo@arm.com>
	Tue, 3 Nov 2020 13:19:52 +0000 (14:19 +0100)
commit	c9a0276840360dd21c91da1a883207833880f124
tree	99114d8e7504af72f5d28b66650523929b69ed30	tree
parent	444655b6f02605ae936426a14ba527795795587b	commit \| diff

arm: Add vld1_lane_bf16 + vldq_lane_bf16 intrinsics

gcc/ChangeLog

2020-10-21 Andrea Corallo <andrea.corallo@arm.com>

* config/arm/arm_neon_builtins.def: Add to LOAD1LANE v4bf, v8bf.
* config/arm/arm_neon.h (vld1_lane_bf16, vld1q_lane_bf16): Add
intrinsics.

gcc/testsuite/ChangeLog

2020-10-21 Andrea Corallo <andrea.corallo@arm.com>

* gcc.target/arm/simd/vld1_lane_bf16_1.c: New testcase.
* gcc.target/arm/simd/vld1_lane_bf16_indices_1.c: Likewise.
* gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c: Likewise.

gcc/config/arm/arm_neon.h		diff \| blob \| history
gcc/config/arm/arm_neon_builtins.def		diff \| blob \| history
gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_1.c	[new file with mode: 0644]	blob
gcc/testsuite/gcc.target/arm/simd/vld1_lane_bf16_indices_1.c	[new file with mode: 0644]	blob
gcc/testsuite/gcc.target/arm/simd/vld1q_lane_bf16_indices_1.c	[new file with mode: 0644]	blob