quicklogic: ABC9 synthesis
authorLofty <dan.ravensloft@gmail.com>
Mon, 12 Apr 2021 09:33:40 +0000 (10:33 +0100)
committerMarcelina Koƛcielnicka <mwk@0x04.net>
Sat, 17 Apr 2021 18:54:58 +0000 (20:54 +0200)
commitdce037a62c5bda9a8256d271d39b06be366120e8
tree67d022cbceb487f5359215d7c9ca51959100f549
parenta58571d0fe8971cb7d3a619a31b2c21be6d75bac
quicklogic: ABC9 synthesis
12 files changed:
techlibs/quicklogic/Makefile.inc
techlibs/quicklogic/abc9_map.v [new file with mode: 0644]
techlibs/quicklogic/abc9_model.v [new file with mode: 0644]
techlibs/quicklogic/abc9_unmap.v [new file with mode: 0644]
techlibs/quicklogic/pp3_cells_sim.v
techlibs/quicklogic/synth_quicklogic.cc
tests/arch/quicklogic/add_sub.ys
tests/arch/quicklogic/counter.ys
tests/arch/quicklogic/fsm.ys
tests/arch/quicklogic/latches.ys
tests/arch/quicklogic/logic.ys
tests/arch/quicklogic/mux.ys