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(parent: 76dabdd) | patch
hook up MSR into MMU (TODO, use a lot less bits)
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 26 Apr 2021 20:45:10 +0000 (21:45 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 26 Apr 2021 20:45:10 +0000 (21:45 +0100)
commite3b3ef9935f000d0a65fa130c0b4c3e3b50f1601
tree094948d90a5ba4d9057ad1ef586bf8df5f61de3dtree
parent76dabddf7fb918dc459aa0d1fa41594033836267commit | diff
hook up MSR into MMU (TODO, use a lot less bits)
src/soc/fu/mmu/fsm.py diff | blob | history
src/soc/fu/mmu/mmu_input_record.py diff | blob | history
src/soc/fu/trap/trap_input_record.py diff | blob | history