Allow the Simulator to handle back-to-back signaling from TestIssuer
authorCesar Strauss <cestrauss@gmail.com>
Sat, 3 Apr 2021 18:40:31 +0000 (15:40 -0300)
committerCesar Strauss <cestrauss@gmail.com>
Sat, 3 Apr 2021 18:40:31 +0000 (15:40 -0300)
commitea41df6fdf78eb36ced514f77af36a0a04589401
tree3d7abc142f94549fa6af14f379c9995fed2f8ee5
parentfad3cd5f00155f88148c608d3abe85e25c416a11
Allow the Simulator to handle back-to-back signaling from TestIssuer

TestIssuer can signal the end of an instruction and, after skipping mask
bits, signal the end of the VL loop, right on the following cycle.
Since there is no handshake between TestIssuer and Simulator, we need to
remove any wait state that would cause the Simulator to miss the one-clock
pulse.
src/soc/simple/test/test_runner.py