add comments about DRAM sync clock being identical to main clock
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 23 Feb 2022 13:14:52 +0000 (13:14 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 23 Feb 2022 13:14:52 +0000 (13:14 +0000)
commitf2357f22dc48692756118a52b9ce3ae5171a07ca
tree875f63c422e1786476a369529e2b3f23e32dc4a9
parent923f907f6b5919ac1b97028a92f4279ed91024ee
add comments about DRAM sync clock being identical to main clock
src/crg.py