create single-stage ALU pipeline, shorten latency on in-order core
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 1 Dec 2021 16:24:50 +0000 (16:24 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 1 Dec 2021 16:24:50 +0000 (16:24 +0000)
commitf700a3e49401f9f6dccde847b880e4af9685829a
treefec6e43239888fb6b69940114d5a27438fd30d15
parent46a317bf788cfbc7b0e8ccde1a4df8db979c9b44
create single-stage ALU pipeline, shorten latency on in-order core
src/soc/fu/alu/pipeline.py