Add and enable async Wishbone bridges async
authorRaptor Engineering Development Team <support@raptorengineering.com>
Thu, 14 Apr 2022 00:55:16 +0000 (19:55 -0500)
committerRaptor Engineering Development Team <support@raptorengineering.com>
Thu, 14 Apr 2022 00:55:16 +0000 (19:55 -0500)
commitb586cc83eea22270d7914e7315565118c18fbf75
treed1fb28c4df9535fd3de83d57526eadbbf9ba7a16
parentaf8454f6c7244da34b95ba43ad775dda333d1d63
Add and enable async Wishbone bridges

Fix simulation with DDR3+SPI
runsimsoc2.sh
simsoc.ys
src/ecp5_crg.py
src/ls2.py