(no commit message)

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index db6ed89205f7177d671e1f96cc3416c042d9d5ad..2408836a0c003fd66bb692a3042b6c0d21668e01 100644 (file)
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -276,7 +276,7 @@ The solution comes in terms of rethinking the definition of a Register
 File.  The typical regfile may be considered to be a multi-ported SRAM
 block, 64 bits wide and usually 32 entries deep, to give 32 64 bit
 registers.  Conceptually, to get our variable element width vectors,
 File.  The typical regfile may be considered to be a multi-ported SRAM
 block, 64 bits wide and usually 32 entries deep, to give 32 64 bit
 registers.  Conceptually, to get our variable element width vectors,

-we may think of the regfile as insead being the following c-based data
+we may think of the regfile as instead being the following c-based data

 structure:
 
     typedef union {
 structure:
 
     typedef union {