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rename mid -> muxid in comment
author
Jacob Lifshay
<programmerjake@gmail.com>
Thu, 11 Jul 2019 09:42:33 +0000
(
02:42
-0700)
committer
Jacob Lifshay
<programmerjake@gmail.com>
Thu, 11 Jul 2019 09:42:33 +0000
(
02:42
-0700)
src/ieee754/fpcommon/roundz.py
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diff --git
a/src/ieee754/fpcommon/roundz.py
b/src/ieee754/fpcommon/roundz.py
index 1585b310934f43d057e658573b82eba22147d126..7704151f34dc79f69e8f99a3bf573c8febf4dd6b 100644
(file)
--- a/
src/ieee754/fpcommon/roundz.py
+++ b/
src/ieee754/fpcommon/roundz.py
@@
-24,7
+24,7
@@
class FPRoundData:
def eq(self, i):
ret = [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
def eq(self, i):
ret = [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
-
self.ctx.eq(i.ctx)]
+ self.ctx.eq(i.ctx)]
return ret
return ret
@@
-50,12
+50,13
@@
class FPRoundMod(Elaboratable):
def elaborate(self, platform):
m = Module()
def elaborate(self, platform):
m = Module()
- m.d.comb += self.out_z.eq(self.i)
# copies m
id, z, out_do_z
- with m.If(~self.i.out_do_z): # bypass wasn't enabled
+ m.d.comb += self.out_z.eq(self.i)
# copies mux
id, z, out_do_z
+ with m.If(~self.i.out_do_z):
# bypass wasn't enabled
with m.If(self.i.roundz):
with m.If(self.i.roundz):
- m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa up
- with m.If(self.i.z.m == self.i.z.m1s): # all 1s
- m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1) # exponent up
+ m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa up
+ with m.If(self.i.z.m == self.i.z.m1s): # all 1s
+ # exponent up
+ m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1)
return m
return m