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test: move to sim = Simulator(dut) instead of context manager.
author
Jean-François Nguyen
<jf@lambdaconcept.com>
Mon, 28 Jun 2021 13:42:45 +0000
(15:42 +0200)
committer
Jean-François Nguyen
<jf@lambdaconcept.com>
Mon, 28 Jun 2021 15:51:38 +0000
(17:51 +0200)
lambdasoc/test/test_periph_base.py
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lambdasoc/test/test_periph_event.py
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lambdasoc/test/test_periph_intc.py
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lambdasoc/test/test_periph_serial.py
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lambdasoc/test/test_periph_sram.py
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lambdasoc/test/test_periph_timer.py
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diff --git
a/lambdasoc/test/test_periph_base.py
b/lambdasoc/test/test_periph_base.py
index 925f49d532d3a8a6cec72555762eff0775074768..c3f59ffcaa32f26aee808b6c72cab55d742814d8 100644
(file)
--- a/
lambdasoc/test/test_periph_base.py
+++ b/
lambdasoc/test/test_periph_base.py
@@
-9,9
+9,10
@@
from ..periph.base import Peripheral, CSRBank, PeripheralBridge
def simulation_test(dut, process):
def simulation_test(dut, process):
- with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
- sim.add_clock(1e-6)
- sim.add_sync_process(process)
+ sim = Simulator(dut)
+ sim.add_clock(1e-6)
+ sim.add_sync_process(process)
+ with sim.write_vcd("test.vcd"):
sim.run()
sim.run()
diff --git
a/lambdasoc/test/test_periph_event.py
b/lambdasoc/test/test_periph_event.py
index 69aacf2923f123c5376698643c7bb0cdb0f006d5..4dfea235e44bd9ee3fccfa8b4333553fc3caae62 100644
(file)
--- a/
lambdasoc/test/test_periph_event.py
+++ b/
lambdasoc/test/test_periph_event.py
@@
-8,9
+8,10
@@
from ..periph.event import *
def simulation_test(dut, process):
def simulation_test(dut, process):
- with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
- sim.add_clock(1e-6)
- sim.add_sync_process(process)
+ sim = Simulator(dut)
+ sim.add_clock(1e-6)
+ sim.add_sync_process(process)
+ with sim.write_vcd("test.vcd"):
sim.run()
sim.run()
diff --git
a/lambdasoc/test/test_periph_intc.py
b/lambdasoc/test/test_periph_intc.py
index add61e9b92a56b99d2708c2bb800e1c95f248776..6aa2f0d220ae2532e9e20439fab9f5423018dc2e 100644
(file)
--- a/
lambdasoc/test/test_periph_intc.py
+++ b/
lambdasoc/test/test_periph_intc.py
@@
-103,6
+103,7
@@
class GenericInterruptControllerTestCase(unittest.TestCase):
yield Delay(1e-6)
self.assertEqual((yield dut.ip), 0b11)
yield Delay(1e-6)
self.assertEqual((yield dut.ip), 0b11)
- with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
- sim.add_process(process)
+ sim = Simulator(dut)
+ sim.add_process(process)
+ with sim.write_vcd("test.vcd"):
sim.run()
sim.run()
diff --git
a/lambdasoc/test/test_periph_serial.py
b/lambdasoc/test/test_periph_serial.py
index 48bc1261a92d99ae331be498f4a5b14dcf56086f..e73c274a3c9aaac2a9904a53b225fb5c786e3bc5 100644
(file)
--- a/
lambdasoc/test/test_periph_serial.py
+++ b/
lambdasoc/test/test_periph_serial.py
@@
-51,7
+51,8
@@
class AsyncSerialPeripheralTestCase(unittest.TestCase):
self.assertEqual(rx_data, 0xab)
yield
self.assertEqual(rx_data, 0xab)
yield
- with Simulator(m, vcd_file=open("test.vcd", "w")) as sim:
- sim.add_clock(1e-6)
- sim.add_sync_process(process)
+ sim = Simulator(m)
+ sim.add_clock(1e-6)
+ sim.add_sync_process(process)
+ with sim.write_vcd("test.vcd"):
sim.run()
sim.run()
diff --git
a/lambdasoc/test/test_periph_sram.py
b/lambdasoc/test/test_periph_sram.py
index 7e4b95e5e2d607da809f169eacf285d7e6c91ae3..266de6d6b7624e2a649d56b569989dd3959a08fe 100644
(file)
--- a/
lambdasoc/test/test_periph_sram.py
+++ b/
lambdasoc/test/test_periph_sram.py
@@
-13,9
+13,10
@@
from ..periph.sram import SRAMPeripheral
def simulation_test(dut, process):
def simulation_test(dut, process):
- with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
- sim.add_clock(1e-6)
- sim.add_sync_process(process)
+ sim = Simulator(dut)
+ sim.add_clock(1e-6)
+ sim.add_sync_process(process)
+ with sim.write_vcd("test.vcd"):
sim.run()
sim.run()
diff --git
a/lambdasoc/test/test_periph_timer.py
b/lambdasoc/test/test_periph_timer.py
index 21a406ab478ea19aeb8d11c2a5e2433810e44654..cdbb9985cd28570ad9ebfe5d3cbdc4066479b936 100644
(file)
--- a/
lambdasoc/test/test_periph_timer.py
+++ b/
lambdasoc/test/test_periph_timer.py
@@
-10,9
+10,10
@@
from ..periph.timer import TimerPeripheral
def simulation_test(dut, process):
def simulation_test(dut, process):
- with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
- sim.add_clock(1e-6)
- sim.add_sync_process(process)
+ sim = Simulator(dut)
+ sim.add_clock(1e-6)
+ sim.add_sync_process(process)
+ with sim.write_vcd("test.vcd"):
sim.run()
sim.run()