+ \begin{itemize}
+ \item Verilog: designed in the 1980s purely for doing unit tests (!)
+ \item VHDL: again, a 1980s-era "Procedural" language (BASIC, Fortran).
+ Does now have "records" which is nice.
+ \item Chisel3 / Scala: OO, but very obscure (20th on index)
+ \item pyrtl: not large enough community
+ \item MyHDL: subset of python only
+ \vspace{9pt}
+ \item Slowly forming a set of criteria: must be OO (python), must have
+ wide adoption (python), must have good well-established
+ programming practices already in place (python), must be
+ easy to learn (python)
+ \item HDL itself although a much smaller community must have the same
+ criteria. Only nmigen meets that criteria.
+
+ \end{itemize}
+}
+
+\frame{\frametitle{Why nmigen?}
+
+ \begin{itemize}
+ \item Uses python to build an AST (Abstract Syntax Tree).
+ Actually hands that over to yosys (to create ILANG file)
+ after which verilog can (if necessary) be created
+ \item Deterministic synthesiseable behaviour (Signals are declared
+ with their reset pattern: no more forgetting "if rst" block).
+ \item python OO programming techniques can be deployed. classes
+ and functions created which pass in parameters which change
+ what HDL is created (IEEE754 FP16 / 32 / 64 for example)
+ \item python-based for-loops can e.g. read CSV files then generate
+ a hierarchical nested suite of HDL Switch / Case statements
+ (this is how the Libre-soc PowerISA decoder is implemented)
+ \item extreme OO abstraction can even be used to create "dynamic
+ partitioned Signals" that have the same operator-overloaded
+ "add", "subtract", "greater-than" operators
+
+ \end{itemize}
+}
+
+\frame{\frametitle{nmigen PowerISA Decoder}
+
+\begin{center}
+\includegraphics[width=0.55\textwidth]{2020-09-09_21-04.png}
+\end{center}
+
+}