- self.br1 = ComputationUnitNoDelay(rwid, 3, self.bgt)
+ aluopwid = 3 # extra bit for immediate mode
+ self.br1 = ComputationUnitNoDelay(rwid, aluopwid, self.bgt)
CompUnitsBase.__init__(self, rwid, [self.br1])
def elaborate(self, platform):
CompUnitsBase.__init__(self, rwid, [self.br1])
def elaborate(self, platform):
self.alu_oper_i = Signal(4, reset_less=True)
self.alu_imm_i = Signal(rwid, reset_less=True)
self.br_oper_i = Signal(4, reset_less=True)
self.alu_oper_i = Signal(4, reset_less=True)
self.alu_imm_i = Signal(rwid, reset_less=True)
self.br_oper_i = Signal(4, reset_less=True)
# Int ALUs and Comp Units
n_int_alus = 5
cua = CompUnitALUs(self.rwid, 3)
# Int ALUs and Comp Units
n_int_alus = 5
cua = CompUnitALUs(self.rwid, 3)
m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cub])
bgt = cub.bgt # get at the branch computation unit
br1 = cub.br1
m.submodules.cu = cu = CompUnitsBase(self.rwid, [cua, cub])
bgt = cub.bgt # get at the branch computation unit
br1 = cub.br1
comb += cua.oper_i.eq(self.alu_oper_i)
comb += cua.imm_i.eq(self.alu_imm_i)
comb += cub.oper_i.eq(self.br_oper_i)
comb += cua.oper_i.eq(self.alu_oper_i)
comb += cua.imm_i.eq(self.alu_imm_i)
comb += cub.oper_i.eq(self.br_oper_i)
# choose a Function-Unit-Group
with m.If((op & (0x3<<2)) != 0): # branch
comb += sc.brissue.insn_i.eq(1)
# choose a Function-Unit-Group
with m.If((op & (0x3<<2)) != 0): # branch
comb += sc.brissue.insn_i.eq(1)
if (op & (0x3<<2)) != 0: # branch
yield dut.brissue.insn_i.eq(1)
yield dut.br_oper_i.eq(Const(op & 0x3, 2))
if (op & (0x3<<2)) != 0: # branch
yield dut.brissue.insn_i.eq(1)
yield dut.br_oper_i.eq(Const(op & 0x3, 2))