cd_sync2x_unbuf = ClockDomain("sync2x_unbuf",
local=False, reset_less=True)
cd_init = ClockDomain("init", local=False)
cd_sync2x_unbuf = ClockDomain("sync2x_unbuf",
local=False, reset_less=True)
cd_init = ClockDomain("init", local=False)
pll.create_clkout(ClockSignal("init"), 25e6)
m.submodules += Instance("ECLKSYNCB",
i_ECLKI = ClockSignal("sync2x_unbuf"),
pll.create_clkout(ClockSignal("init"), 25e6)
m.submodules += Instance("ECLKSYNCB",
i_ECLKI = ClockSignal("sync2x_unbuf"),
reset_ok = Signal(reset_less=True)
m.d.comb += reset_ok.eq(~pll.locked|~pod_done)
m.d.comb += ResetSignal("init").eq(reset_ok)
reset_ok = Signal(reset_less=True)
m.d.comb += reset_ok.eq(~pll.locked|~pod_done)
m.d.comb += ResetSignal("init").eq(reset_ok)
- m.d.comb += ResetSignal("sync").eq(reset_ok|self.ddr_clk_reset)
- m.d.comb += ResetSignal("dramsync").eq(reset_ok|self.ddr_clk_reset)
+ m.d.comb += ResetSignal("sync").eq(reset_ok)
+ m.d.comb += ResetSignal("dramsync").eq(reset_ok)