- # distinguish op type (ld/st)
- self.is_ld_i = Signal(reset_less=True)
- self.is_st_i = Signal(reset_less=True)
+ # distinguish op type (ld/st/dcbz)
+ self.is_ld_i = Signal(reset_less=True)
+ self.is_st_i = Signal(reset_less=True)
+ self.is_dcbz_i = Signal(reset_less=True)
+ self.is_dcbz = self.is_dcbz_i # renamed signal hack
# LD/ST data length (TODO: other things may be needed)
self.data_len = Signal(4, reset_less=True)
# LD/ST data length (TODO: other things may be needed)
self.data_len = Signal(4, reset_less=True)
self.is_nc = Signal() # no cacheing
self.msr_pr = Signal() # 1==virtual, 0==privileged
# mmu
self.mmu_done = Signal() # keep for now
self.is_nc = Signal() # no cacheing
self.msr_pr = Signal() # 1==virtual, 0==privileged
# mmu
self.mmu_done = Signal() # keep for now
# dcache
self.ldst_error = Signal()
## Signalling ld/st error - NC cache hit, TLB miss, prot/RC failure
# dcache
self.ldst_error = Signal()
## Signalling ld/st error - NC cache hit, TLB miss, prot/RC failure
def set_rd_addr(self, m, addr, mask, misalign, msr_pr): pass
def set_wr_data(self, m, data, wen): pass
def get_rd_data(self, m): pass
def set_rd_addr(self, m, addr, mask, misalign, msr_pr): pass
def set_wr_data(self, m, data, wen): pass
def get_rd_data(self, m): pass
m.submodules.st_active = st_active = SRLatch(False, name="st_active")
m.submodules.st_done = st_done = SRLatch(False, name="st_done")
m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
m.submodules.st_active = st_active = SRLatch(False, name="st_active")
m.submodules.st_done = st_done = SRLatch(False, name="st_done")
m.submodules.ld_active = ld_active = SRLatch(False, name="ld_active")
m.submodules.reset_l = reset_l = SRLatch(True, name="reset")
m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
m.submodules.reset_l = reset_l = SRLatch(True, name="reset")
m.submodules.adrok_l = adrok_l = SRLatch(False, name="addr_acked")
m.submodules.busy_l = busy_l = SRLatch(False, name="busy")
# activate mode: only on "edge"
comb += ld_active.s.eq(rising_edge(m, lds)) # activate LD mode
comb += st_active.s.eq(rising_edge(m, sts)) # activate ST mode
# activate mode: only on "edge"
comb += ld_active.s.eq(rising_edge(m, lds)) # activate LD mode
comb += st_active.s.eq(rising_edge(m, sts)) # activate ST mode
# LD/ST requested activates "busy" (only if not already busy)
with m.If(self.pi.is_ld_i | self.pi.is_st_i):
# LD/ST requested activates "busy" (only if not already busy)
with m.If(self.pi.is_ld_i | self.pi.is_st_i):
+ # if now in "DCBZ" mode: wait for addr_ok, then send the address out
+ # to memory, acknowledge address, and send out LD data
+ with m.If(dcbz_active.q):
+ self.set_dcbz_addr(m, pi.addr.data)
+
# if now in "ST" mode: likewise do the same but with "ST"
# to memory, acknowledge address, and send out LD data
with m.If(st_active.q):
# if now in "ST" mode: likewise do the same but with "ST"
# to memory, acknowledge address, and send out LD data
with m.If(st_active.q):
comb += reset_l.r.eq(1) # clear reset
comb += adrok_l.r.eq(1) # address reset
comb += st_done.r.eq(1) # store done reset
comb += reset_l.r.eq(1) # clear reset
comb += adrok_l.r.eq(1) # address reset
comb += st_done.r.eq(1) # store done reset