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periph.serial: use buffered FIFOs to help BRAM inference.
author
Jean-François Nguyen
<jf@lambdaconcept.com>
Mon, 28 Jun 2021 14:18:10 +0000
(16:18 +0200)
committer
Jean-François Nguyen
<jf@lambdaconcept.com>
Mon, 28 Jun 2021 15:52:37 +0000
(17:52 +0200)
lambdasoc/periph/serial.py
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diff --git
a/lambdasoc/periph/serial.py
b/lambdasoc/periph/serial.py
index 5176c136e14d469766d6e01a9e0e6aad41794d4f..a25c78d8f317606f2e20c8ff807a7b906ee8100e 100644
(file)
--- a/
lambdasoc/periph/serial.py
+++ b/
lambdasoc/periph/serial.py
@@
-1,5
+1,5
@@
from nmigen import *
from nmigen import *
-from nmigen.lib.fifo import SyncFIFO
+from nmigen.lib.fifo import SyncFIFO
Buffered
from nmigen_stdio.serial import AsyncSerial
from nmigen_stdio.serial import AsyncSerial
@@
-65,9
+65,9
@@
class AsyncSerialPeripheral(Peripheral, Elaboratable):
def __init__(self, *, rx_depth=16, tx_depth=16, **kwargs):
super().__init__()
def __init__(self, *, rx_depth=16, tx_depth=16, **kwargs):
super().__init__()
- self._phy = AsyncSerial(**kwargs)
- self._rx_fifo = SyncFIFO(width=self._phy.rx.data.width, depth=rx_depth)
- self._tx_fifo = SyncFIFO(width=self._phy.tx.data.width, depth=tx_depth)
+ self._phy = AsyncSerial(
data_bits=data_bits,
**kwargs)
+ self._rx_fifo = SyncFIFO
Buffered
(width=self._phy.rx.data.width, depth=rx_depth)
+ self._tx_fifo = SyncFIFO
Buffered
(width=self._phy.tx.data.width, depth=tx_depth)
bank = self.csr_bank()
self._divisor = bank.csr(self._phy.divisor.width, "rw")
bank = self.csr_bank()
self._divisor = bank.csr(self._phy.divisor.width, "rw")