+ # get predicate mask
+ srcmask = dstmask = 0xffff_ffff_ffff_ffff
+ if self.is_svp64_mode:
+ pmode = yield self.dec2.rm_dec.predmode
+ sv_ptype = yield self.dec2.dec.op.SV_Ptype
+ srcpred = yield self.dec2.rm_dec.srcpred
+ dstpred = yield self.dec2.rm_dec.dstpred
+ if pmode == SVP64PredMode.INT.value:
+ srcmask = dstmask = get_predint(self.gpr, dstpred)
+ if sv_ptype == SVPtype.P2.value:
+ srcmask = get_predint(srcpred)
+ print (" pmode", pmode)
+ print (" ptype", sv_ptype)
+ print (" srcmask", bin(srcmask))
+ print (" dstmask", bin(dstmask))
+
+ # okaaay, so here we simply advance srcstep (TODO dststep)
+ # until the predicate mask has a "1" bit... or we run out of VL
+ # let srcstep==VL be the indicator to move to next instruction
+ while (((1<<srcstep) & srcmask) == 0) and (srcstep != vl):
+ print (" skip", bin(1<<srcstep))
+ srcstep += 1
+
+ # update SVSTATE with new srcstep
+ self.svstate.srcstep[0:7] = srcstep
+ self.namespace['SVSTATE'] = self.svstate.spr
+ yield self.dec2.state.svstate.eq(self.svstate.spr.value)
+ yield Settle() # let decoder update
+ srcstep = self.svstate.srcstep.asint(msb0=True)
+ print (" srcstep", srcstep)
+
+ # check if end reached (we let srcstep overrun, above)
+ # nothing needs doing (TODO zeroing): just do next instruction
+ if srcstep == vl:
+ self.svp64_reset_loop()
+ self.update_pc_next()
+ return
+