+ # test all combinations of masked input ports
+ yield from op.issue([5, 2, 0], MicrOp.OP_NOP, [0],
+ rdmaskn=[1, 0, 0],
+ src_delays=[0, 2, 1], dest_delays=[0])
+ yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [9],
+ rdmaskn=[0, 1, 0],
+ src_delays=[2, 1, 0], dest_delays=[2])
+ yield from op.issue([5, 2, 0], MicrOp.OP_NOP, [5],
+ rdmaskn=[0, 0, 1],
+ src_delays=[2, 1, 0], dest_delays=[2])
+ yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [9],
+ rdmaskn=[0, 1, 1],
+ src_delays=[2, 1, 0], dest_delays=[2])
+ yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [0],
+ rdmaskn=[1, 1, 0],
+ src_delays=[2, 1, 0], dest_delays=[2])
+ yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [0],
+ rdmaskn=[1, 1, 1],
+ src_delays=[2, 1, 0], dest_delays=[2])