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fix dmi reg read
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Thu, 13 Aug 2020 21:44:29 +0000
(22:44 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Thu, 13 Aug 2020 21:44:29 +0000
(22:44 +0100)
src/soc/simple/issuer.py
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diff --git
a/src/soc/simple/issuer.py
b/src/soc/simple/issuer.py
index 42bb5977608de57079c2219e36d59c02a056de4d..bf28f86f60e099421ba1fe412b9abe99558f9f3f 100644
(file)
--- a/
src/soc/simple/issuer.py
+++ b/
src/soc/simple/issuer.py
@@
-65,7
+65,8
@@
class TestIssuer(Elaboratable):
self.state_r_msr = self.core.regs.rf['state'].r_ports['msr'] # MSR rd
# DMI interface access
self.state_r_msr = self.core.regs.rf['state'].r_ports['msr'] # MSR rd
# DMI interface access
- self.int_r = self.core.regs.rf['int'].r_ports['dmi'] # INT read
+ intrf = self.core.regs.rf['int']
+ self.int_r = intrf.r_ports['dmi'] # INT read
# hack method of keeping an eye on whether branch/trap set the PC
self.state_nia = self.core.regs.rf['state'].w_ports['nia']
# hack method of keeping an eye on whether branch/trap set the PC
self.state_nia = self.core.regs.rf['state'].w_ports['nia']
@@
-82,6
+83,7
@@
class TestIssuer(Elaboratable):
# convenience
dmi = dbg.dmi
d_reg = dbg.dbg_gpr
# convenience
dmi = dbg.dmi
d_reg = dbg.dbg_gpr
+ intrf = self.core.regs.rf['int']
# clock delay power-on reset
cd_por = ClockDomain(reset_less=True)
# clock delay power-on reset
cd_por = ClockDomain(reset_less=True)
@@
-229,11
+231,11
@@
class TestIssuer(Elaboratable):
with m.If(d_reg.req): # request for regfile access being made
# TODO: error-check this
# XXX should this be combinatorial? sync better?
with m.If(d_reg.req): # request for regfile access being made
# TODO: error-check this
# XXX should this be combinatorial? sync better?
- if
hasattr(self.int_r, "ren")
:
+ if
intrf.unary
:
comb += self.int_r.ren.eq(1<<d_reg.addr)
else:
comb += self.int_r.addr.eq(d_reg.addr)
comb += self.int_r.ren.eq(1<<d_reg.addr)
else:
comb += self.int_r.addr.eq(d_reg.addr)
- comb += self.int_r.en.eq(1)
+ comb += self.int_r.
r
en.eq(1)
comb += d_reg.data.eq(self.int_r.data_o)
comb += d_reg.ack.eq(1)
comb += d_reg.data.eq(self.int_r.data_o)
comb += d_reg.ack.eq(1)