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remove "sv." and replace with "sv" in all SVP64Asm
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sun, 14 Mar 2021 14:54:45 +0000
(14:54 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sun, 14 Mar 2021 14:54:45 +0000
(14:54 +0000)
src/soc/decoder/isa/test_caller_setvl.py
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|
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|
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src/soc/decoder/isa/test_caller_svp64.py
patch
|
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|
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src/soc/fu/alu/test/svp64_cases.py
patch
|
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src/soc/sv/trans/svp64.py
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diff --git
a/src/soc/decoder/isa/test_caller_setvl.py
b/src/soc/decoder/isa/test_caller_setvl.py
index ad7991f18febae289809c53402f6d04841537fc6..cb21563542ee210c18b03adbc628c7575b7e4fd8 100644
(file)
--- a/
src/soc/decoder/isa/test_caller_setvl.py
+++ b/
src/soc/decoder/isa/test_caller_setvl.py
@@
-49,7
+49,7
@@
class DecoderTestCase(FHDLTestCase):
# 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
# 2 = 6 + 10 => 0x3334 = 0x2223+0x1111
isa = SVP64Asm(["setvl 3, 0, 1, 1, 1",
# 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
# 2 = 6 + 10 => 0x3334 = 0x2223+0x1111
isa = SVP64Asm(["setvl 3, 0, 1, 1, 1",
- 'sv
.
add 1.v, 5.v, 9.v'
+ 'svadd 1.v, 5.v, 9.v'
])
lst = list(isa)
print ("listing", lst)
])
lst = list(isa)
print ("listing", lst)
diff --git
a/src/soc/decoder/isa/test_caller_svp64.py
b/src/soc/decoder/isa/test_caller_svp64.py
index 7875dc089c638d717c5ea87c45288b837aaf4c93..44e71049fd94eb51d2606255de6edc82f4714a6d 100644
(file)
--- a/
src/soc/decoder/isa/test_caller_svp64.py
+++ b/
src/soc/decoder/isa/test_caller_svp64.py
@@
-26,8
+26,8
@@
class DecoderTestCase(FHDLTestCase):
"addi 2, 0, 0x0008",
"addi 5, 0, 0x1234",
"addi 6, 0, 0x1235",
"addi 2, 0, 0x0008",
"addi 5, 0, 0x1234",
"addi 6, 0, 0x1235",
- "sv
.
stw 5.v, 0(1.v)",
- "sv
.
lwz 9.v, 0(1.v)"])
+ "svstw 5.v, 0(1.v)",
+ "svlwz 9.v, 0(1.v)"])
lst = list(lst)
# SVSTATE (in this case, VL=2)
lst = list(lst)
# SVSTATE (in this case, VL=2)
@@
-46,7
+46,7
@@
class DecoderTestCase(FHDLTestCase):
# adds:
# 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
# 2 = 6 + 10 => 0x3334 = 0x2223+0x1111
# adds:
# 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
# 2 = 6 + 10 => 0x3334 = 0x2223+0x1111
- isa = SVP64Asm(['sv
.
add 1.v, 5.v, 9.v'
+ isa = SVP64Asm(['svadd 1.v, 5.v, 9.v'
])
lst = list(isa)
print ("listing", lst)
])
lst = list(isa)
print ("listing", lst)
@@
-75,7
+75,7
@@
class DecoderTestCase(FHDLTestCase):
# adds:
# 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
# r1 is scalar so ENDS EARLY
# adds:
# 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
# r1 is scalar so ENDS EARLY
- isa = SVP64Asm(['sv
.
add 1, 5.v, 9.v'
+ isa = SVP64Asm(['svadd 1, 5.v, 9.v'
])
lst = list(isa)
print ("listing", lst)
])
lst = list(isa)
print ("listing", lst)
@@
-103,7
+103,7
@@
class DecoderTestCase(FHDLTestCase):
# adds:
# 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
# 2 = 5 + 10 => 0x5432 = 0x4321+0x1111
# adds:
# 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
# 2 = 5 + 10 => 0x5432 = 0x4321+0x1111
- isa = SVP64Asm(['sv
.
add 1.v, 5, 9.v'
+ isa = SVP64Asm(['svadd 1.v, 5, 9.v'
])
lst = list(isa)
print ("listing", lst)
])
lst = list(isa)
print ("listing", lst)
@@
-131,7
+131,7
@@
class DecoderTestCase(FHDLTestCase):
def test_sv_add_vl_0(self):
# adds:
# none because VL is zer0
def test_sv_add_vl_0(self):
# adds:
# none because VL is zer0
- isa = SVP64Asm(['sv
.
add 1, 5.v, 9.v'
+ isa = SVP64Asm(['svadd 1, 5.v, 9.v'
])
lst = list(isa)
print ("listing", lst)
])
lst = list(isa)
print ("listing", lst)
@@
-158,7
+158,7
@@
class DecoderTestCase(FHDLTestCase):
# adds when Rc=1: TODO CRs higher up
# 1 = 5 + 9 => 0 = -1+1 CR0=0b100
# 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010
# adds when Rc=1: TODO CRs higher up
# 1 = 5 + 9 => 0 = -1+1 CR0=0b100
# 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010
- isa = SVP64Asm(['sv
.
add. 1.v, 5.v, 9.v'
+ isa = SVP64Asm(['svadd. 1.v, 5.v, 9.v'
])
lst = list(isa)
print ("listing", lst)
])
lst = list(isa)
print ("listing", lst)
diff --git
a/src/soc/fu/alu/test/svp64_cases.py
b/src/soc/fu/alu/test/svp64_cases.py
index dd8e0ff797a6d0b6cdd2042e63a43eefe1fb8d89..52b1ac0606e960d1e0d64c0bed5d8fda5ccabf5b 100644
(file)
--- a/
src/soc/fu/alu/test/svp64_cases.py
+++ b/
src/soc/fu/alu/test/svp64_cases.py
@@
-11,7
+11,7
@@
class SVP64ALUTestCase(TestAccumulatorBase):
# adds:
# 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
# 2 = 6 + 10 => 0x3334 = 0x2223 + 0x1111
# adds:
# 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
# 2 = 6 + 10 => 0x3334 = 0x2223 + 0x1111
- isa = SVP64Asm(['sv
.
add 1.v, 5.v, 9.v'])
+ isa = SVP64Asm(['svadd 1.v, 5.v, 9.v'])
lst = list(isa)
print("listing", lst)
lst = list(isa)
print("listing", lst)
@@
-33,7
+33,7
@@
class SVP64ALUTestCase(TestAccumulatorBase):
def case_2_sv_add_scalar(self):
# adds:
# 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
def case_2_sv_add_scalar(self):
# adds:
# 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
- isa = SVP64Asm(['sv
.
add 1, 5, 9'])
+ isa = SVP64Asm(['svadd 1, 5, 9'])
lst = list(isa)
print("listing", lst)
lst = list(isa)
print("listing", lst)
@@
-58,7
+58,7
@@
class SVP64ALUTestCase(TestAccumulatorBase):
def case_3_sv_check_extra(self):
# adds:
# 13 = 10 + 7 => 0x4242 = 0x1230 + 0x3012
def case_3_sv_check_extra(self):
# adds:
# 13 = 10 + 7 => 0x4242 = 0x1230 + 0x3012
- isa = SVP64Asm(['sv
.
add 13.v, 10.v, 7.v'])
+ isa = SVP64Asm(['svadd 13.v, 10.v, 7.v'])
lst = list(isa)
print("listing", lst)
lst = list(isa)
print("listing", lst)
@@
-80,7
+80,7
@@
class SVP64ALUTestCase(TestAccumulatorBase):
# 1 = 5 + 9 => 0 = -1+1 CR0=0b100
# 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010
# 1 = 5 + 9 => 0 = -1+1 CR0=0b100
# 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010
- isa = SVP64Asm(['sv
.
add. 1.v, 5.v, 9.v'])
+ isa = SVP64Asm(['svadd. 1.v, 5.v, 9.v'])
lst = list(isa)
print("listing", lst)
lst = list(isa)
print("listing", lst)
@@
-104,7
+104,7
@@
class SVP64ALUTestCase(TestAccumulatorBase):
# adds:
# 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
isa = SVP64Asm([
# adds:
# 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
isa = SVP64Asm([
- 'sv
.
add 13.v, 10.v, 7.v', # skipped, because VL == 0
+ 'svadd 13.v, 10.v, 7.v', # skipped, because VL == 0
'add 1, 5, 9'
])
lst = list(isa)
'add 1, 5, 9'
])
lst = list(isa)
@@
-135,8
+135,8
@@
class SVP64ALUTestCase(TestAccumulatorBase):
# 14 = 11 + 8 => 0x3012 = 0x3012 + 0x0000
# 15 = 12 + 9 => 0x1234 = 0x0000 + 0x1234
isa = SVP64Asm([
# 14 = 11 + 8 => 0x3012 = 0x3012 + 0x0000
# 15 = 12 + 9 => 0x1234 = 0x0000 + 0x1234
isa = SVP64Asm([
- 'sv
.
add 1.v, 5.v, 9.v',
- 'sv
.
add 13.v, 10.v, 7.v'
+ 'svadd 1.v, 5.v, 9.v',
+ 'svadd 13.v, 10.v, 7.v'
])
lst = list(isa)
print("listing", lst)
])
lst = list(isa)
print("listing", lst)
@@
-162,7
+162,7
@@
class SVP64ALUTestCase(TestAccumulatorBase):
# adds:
# 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
# r1 is scalar so ENDS EARLY
# adds:
# 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
# r1 is scalar so ENDS EARLY
- isa = SVP64Asm(['sv
.
add 1, 5.v, 9.v'])
+ isa = SVP64Asm(['svadd 1, 5.v, 9.v'])
lst = list(isa)
print("listing", lst)
lst = list(isa)
print("listing", lst)
@@
-184,7
+184,7
@@
class SVP64ALUTestCase(TestAccumulatorBase):
# adds:
# 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
# 2 = 5 + 10 => 0x5432 = 0x4321+0x1111
# adds:
# 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
# 2 = 5 + 10 => 0x5432 = 0x4321+0x1111
- isa = SVP64Asm(['sv
.
add 1.v, 5, 9.v'])
+ isa = SVP64Asm(['svadd 1.v, 5, 9.v'])
lst = list(isa)
print("listing", lst)
lst = list(isa)
print("listing", lst)
diff --git
a/src/soc/sv/trans/svp64.py
b/src/soc/sv/trans/svp64.py
index 7fb01acd249f06dea514e726a4a63c976621cfe5..21182295e3874df6977f51c00b38fd18ebd45f97 100644
(file)
--- a/
src/soc/sv/trans/svp64.py
+++ b/
src/soc/sv/trans/svp64.py
@@
-179,10
+179,10
@@
class SVP64Asm:
continue
# identify if is a svp64 mnemonic
continue
# identify if is a svp64 mnemonic
- if not opcode.startswith('sv
.
'):
+ if not opcode.startswith('sv'):
yield insn # unaltered
continue
yield insn # unaltered
continue
- opcode = opcode[
3:] # strip leading "sv.
"
+ opcode = opcode[
2:] # strip leading "sv
"
# start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
opmodes = opcode.split("/") # split at "/"
# start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
opmodes = opcode.split("/") # split at "/"