- if alg_op is Operation.UDivRem:
- if divisor_radicand == 0:
- return
- quotient_root, remainder = div_rem(dividend,
- divisor_radicand,
- bit_width * 3,
- False)
- remainder <<= fract_width
- elif alg_op is Operation.SqrtRem:
- root_remainder = fixed_sqrt(Fixed.from_bits(divisor_radicand,
- fract_width,
- bit_width,
- False))
- quotient_root = root_remainder.root.bits
- remainder = root_remainder.remainder.bits << fract_width
- else:
- assert alg_op is Operation.RSqrtRem
- if divisor_radicand == 0:
- return
- root_remainder = fixed_rsqrt(Fixed.from_bits(divisor_radicand,
- fract_width,
- bit_width,
- False))
- quotient_root = root_remainder.root.bits
- remainder = root_remainder.remainder.bits
- if quotient_root >= (1 << bit_width):
- return
+ obj = FixedUDivRemSqrtRSqrt(dividend,
+ divisor_radicand,
+ alg_op,
+ bit_width,
+ fract_width,
+ core_config.log2_radix)
+ obj.calculate()