clarify quirks

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index 448d6b0b69b9bebc6e89ef44212ec0b499725a20..bd87088509fac71918d8dad974ebaac9400d57ef 100644 (file)
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -11,8 +11,8 @@ as a concept became popular.
    are the sole exclusive bedrock.
 2. No scalar instruction ever deviates in its encoding or meaning
    just because it is prefixed (semantic caveats below)
    are the sole exclusive bedrock.
 2. No scalar instruction ever deviates in its encoding or meaning
    just because it is prefixed (semantic caveats below)

-3. A hardware-level for-loop makes vector elements 100% synonymous
-   with scalar instructions (the suffix)
+3. A hardware-level for-loop (the prefix) makes vector elements
+   100% synonymous with scalar instructions (the suffix)

 
 How can a Vector ISA even exist when no actual Vector instructions
 are permitted to be added? It comes down to the strict RISC abstraction.
 
 How can a Vector ISA even exist when no actual Vector instructions
 are permitted to be added? It comes down to the strict RISC abstraction.