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dont have to but test latchregister incoming is a Record
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sun, 22 Mar 2020 14:30:29 +0000
(14:30 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sun, 22 Mar 2020 14:30:29 +0000
(14:30 +0000)
src/nmutil/latch.py
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diff --git
a/src/nmutil/latch.py
b/src/nmutil/latch.py
index 5f3a0c01edc73fa0bc2559da4378e94df9a62885..7d6a1efe22c881585a626e397590337186f6ef1b 100644
(file)
--- a/
src/nmutil/latch.py
+++ b/
src/nmutil/latch.py
@@
-1,6
+1,6
@@
from nmigen.compat.sim import run_simulation
from nmigen.cli import verilog, rtlil
from nmigen.compat.sim import run_simulation
from nmigen.cli import verilog, rtlil
-from nmigen import Signal, Module, Const, Elaboratable
+from nmigen import
Record,
Signal, Module, Const, Elaboratable
""" jk latch
""" jk latch
@@
-22,7
+22,11
@@
endmodule
"""
def latchregister(m, incoming, outgoing, settrue, name=None):
"""
def latchregister(m, incoming, outgoing, settrue, name=None):
- reg = Signal.like(incoming, name=name) # make reg same as input. reset OK.
+ # make reg same as input. reset OK.
+ if isinstance(incoming, Record):
+ reg = Record.like(incoming, name=name)
+ else:
+ reg = Signal.like(incoming, name=name)
with m.If(settrue): # pass in some kind of expression/condition here
m.d.sync += reg.eq(incoming) # latch input into register
m.d.comb += outgoing.eq(incoming) # return input (combinatorial)
with m.If(settrue): # pass in some kind of expression/condition here
m.d.sync += reg.eq(incoming) # latch input into register
m.d.comb += outgoing.eq(incoming) # return input (combinatorial)