- # create 25 mhz "init" clock, straight (no 2x phase stuff)
- cd_init = ClockDomain("init", local=False)
- pll.create_clkout(ClockSignal("init"), 25e6)
- m.domains += cd_init
- m.d.comb += ResetSignal("init").eq(reset_ok)
-
- # Generating sync2x and sync from extclk, which is *only* how
- # xdr=4 can be requested on the sync domain
- self.phase2_domain(m, pll, "sync", self.sys_clk_freq)
+ # single or double main sync clock domain. double needs a 2nd PLL
+ # to match up with the CLKESYNCB, one per quadrant inside the ECP5
+ if self.dram_clk_freq is not None:
+ m.domains += ClockDomain("sync_unbuf", local=False, reset_less=True)
+ m.domains += ClockDomain("sync", local=False)
+ pll.create_clkout(ClockSignal("sync_unbuf"), self.sys_clk_freq)
+ m.d.comb += ClockSignal("sync").eq(ClockSignal("sync_unbuf"))
+ else:
+ # Generating sync2x and sync from extclk, which is *only* how
+ # xdr=4 can be requested on the sync domain. also do not request
+ # an edge-clock-stop
+ self.phase2_domain(m, pll, "sync", self.sys_clk_freq, True)
+ m.d.comb += ResetSignal("sync2x").eq(reset_ok)