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loadstore.py: add function set_dcbz_addr
author
Tobias Platen
<tplaten@posteo.de>
Sat, 2 Oct 2021 12:50:00 +0000
(14:50 +0200)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Fri, 8 Oct 2021 13:30:35 +0000
(14:30 +0100)
src/soc/fu/ldst/loadstore.py
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diff --git
a/src/soc/fu/ldst/loadstore.py
b/src/soc/fu/ldst/loadstore.py
index d9f0c14a5d293e91a2fc053e182b7e940cdc8394..6cfc7c01a93a9d7d61567e72c2f4cbebc10bb845 100644
(file)
--- a/
src/soc/fu/ldst/loadstore.py
+++ b/
src/soc/fu/ldst/loadstore.py
@@
-119,6
+119,17
@@
class LoadStore1(PortInterfaceBase):
#self.nia = Signal(64)
#self.srr1 = Signal(16)
#self.nia = Signal(64)
#self.srr1 = Signal(16)
+ def set_dcbz_addr(self, m, addr):
+ m.d.comb += self.req.load.eq(0) #not a load operation
+ m.d.comb += self.req.dcbz.eq(1)
+ #m.d.comb += self.req.byte_sel.eq(mask)
+ m.d.comb += self.req.addr.eq(addr)
+ m.d.comb += Display("set_dcbz_addr %i",addr)
+ #m.d.comb += self.req.priv_mode.eq(~msr_pr) # not-problem ==> priv
+ #m.d.comb += self.req.virt_mode.eq(msr_pr) # problem-state ==> virt
+ #m.d.comb += self.req.align_intr.eq(misalign)
+ return None
+
def set_wr_addr(self, m, addr, mask, misalign, msr_pr):
m.d.comb += self.req.load.eq(0) # store operation
m.d.comb += self.req.byte_sel.eq(mask)
def set_wr_addr(self, m, addr, mask, misalign, msr_pr):
m.d.comb += self.req.load.eq(0) # store operation
m.d.comb += self.req.byte_sel.eq(mask)