add expired patent

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index 1f479badad0209ee49ebd85864e2376ee9613fb4..6599f930bf7f6aa597e8405b61cc967fecb381b7 100644 (file)
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -477,6 +477,8 @@ In Section 12.3 riscv-isa manual V2.3-draft it is noted the comments on
 page 76, "For virtual memory systems some data accesses could be resident
 in physical memory and some not".  The interesting question then arises:
 how does RVV deal with the exact same scenario?
 page 76, "For virtual memory systems some data accesses could be resident
 in physical memory and some not".  The interesting question then arises:
 how does RVV deal with the exact same scenario?

+Expired U.S. Patent 5895501 (Filing Date Sep 3 1996) describes a method
+of detecting early page / segmentation faults.

 
 # Note on implementation of parallelism
 
 
 # Note on implementation of parallelism
 


@@ -1338,3 +1340,5 @@ by *introducing* deliberate latency into the execution phase.
 * Multi-ported VLIW Register File Implementation <https://ce-publications.et.tudelft.nl/publications/1517_multiple_contexts_in_a_multiported_vliw_register_file_impl.pdf>
 * Fast context save/restore proposal <https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/57F823FA.6030701%40gmail.com>
 * Register File Bank Cacheing <https://www.princeton.edu/~rblee/ELE572Papers/MultiBankRegFile_ISCA2000.pdf>
 * Multi-ported VLIW Register File Implementation <https://ce-publications.et.tudelft.nl/publications/1517_multiple_contexts_in_a_multiported_vliw_register_file_impl.pdf>
 * Fast context save/restore proposal <https://groups.google.com/a/groups.riscv.org/d/msgid/isa-dev/57F823FA.6030701%40gmail.com>
 * Register File Bank Cacheing <https://www.princeton.edu/~rblee/ELE572Papers/MultiBankRegFile_ISCA2000.pdf>

+* Expired Patent on Vector Virtual Memory solutions
+  <https://patentimages.storage.googleapis.com/fc/f6/e2/2cbee92fcd8743/US5895501.pdf?