+class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends LazyModule {
+ val ranges = AddressRange.fromSets(c.address)
+ require (ranges.size == 1, "DDR range must be contiguous")
+ val offset = ranges.head.base
+ val depth = ranges.head.size
+ require((depth==0x40000000L) || (depth==0x100000000L)) //1GB or 4GB depth
+