+Memory access remains exactly the same: the effects of `MSR.LE` remain exactly the same,
+affecting **only** the Load and Store memory-register operation byte-order,
+and having nothing to do with the
+ordering of the contents of register files or register-register operations.
+
+Whilst the bits within the GPRs and FPRs are expected to be MSB0-ordered and for
+numbering to be sequentially incremental the element offset numbering is naturally
+**LSB0-sequentially-incrementing from zero not MSB0-incrementing.** Expressed in
+MSB0-numbering SVP64 is unnecessarily complex to understand: subtractions from 63, 31,
+15 and 7 become a hostile minefield. Therefore for the purposes of this section
+**LSB0 numbering is assumed** and it is up to the reader to translate to MSB0 numbering.
+
+The Canonical specification for how element-sequential numbering and element-width
+overrides is defined is expressed in the following c structure, assuming a Little-Endian
+system, and naturally using LSB0 numbering everywhere because the ANSI c specification
+is inherently LSB0: