- # Delayed from the start of transaction by 1 clk cycle
- with m.If(new_transaction):
- # Update the GPIO configs with sent parameters
- with m.If(bus.we):
- for i in range(len(bus.sel)):
- GPIO_num = Signal(16) # fixed for now
- comb += GPIO_num.eq(bus.adr*len(bus.sel)+i)
- with m.If(bus.sel[i]):
- sync += gpio_ports[GPIO_num].oe.eq(wr_multi[i].oe)
- sync += gpio_ports[GPIO_num].puen.eq(wr_multi[i].puen)
- sync += gpio_ports[GPIO_num].pden.eq(wr_multi[i].pden)
- with m.If (wr_multi[i].oe):
- sync += gpio_ports[GPIO_num].o.eq(wr_multi[i].io)
- with m.Else():
- sync += gpio_ports[GPIO_num].o.eq(0)
- sync += gpio_ports[GPIO_num].bank.eq(wr_multi[i].bank)
- sync += wb_ack.eq(1) # ack after latching data
- # No need as rd data is can be outputed on the first clk
- # with m.Else():
- # sync += wb_ack.eq(1) # Delay ack until rd data is ready!