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add option to specify UART16550 width (32/8)
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 15 Feb 2022 15:28:48 +0000
(15:28 +0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 15 Feb 2022 15:28:48 +0000
(15:28 +0000)
src/soc/bus/uart_16550.py
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diff --git
a/src/soc/bus/uart_16550.py
b/src/soc/bus/uart_16550.py
index 87779a53895e0af5571e099fa3d027cab8185c3b..916c2fd44a8fb9f659f3763db8ba82dc44664d06 100644
(file)
--- a/
src/soc/bus/uart_16550.py
+++ b/
src/soc/bus/uart_16550.py
@@
-22,7
+22,7
@@
class UART16550(Elaboratable):
UART16550.add_verilog_source
"""
UART16550.add_verilog_source
"""
- def __init__(self, bus=None, features=None, name=None):
+ def __init__(self, bus=None, features=None, name=None
, data_width=32
):
if name is not None:
# convention: give the name in the format "name_number"
self.idx = int(name.split("_")[-1])
if name is not None:
# convention: give the name in the format "name_number"
self.idx = int(name.split("_")[-1])
@@
-35,12
+35,13
@@
class UART16550(Elaboratable):
features = frozenset()
if bus is None:
bus = Interface(addr_width=5,
features = frozenset()
if bus is None:
bus = Interface(addr_width=5,
- data_width=
32
,
+ data_width=
data_width
,
features=features,
granularity=8,
name=name+"_wb_%d" % self.idx)
self.bus = bus
features=features,
granularity=8,
name=name+"_wb_%d" % self.idx)
self.bus = bus
- assert len(self.bus.dat_r) == 32, "bus width must be 32"
+ assert len(self.bus.dat_r) == data_width, \
+ "bus width must be %d" % data_width
# IRQ for data buffer receive/xmit
self.irq = Signal()
# IRQ for data buffer receive/xmit
self.irq = Signal()
@@
-117,7
+118,7
@@
def create_verilog(dut, ports, test_name):
if __name__ == "__main__":
if __name__ == "__main__":
- uart = UART16550(name="uart_0")
+ uart = UART16550(name="uart_0"
, data_width=8
)
create_ilang(uart, [uart.bus.cyc, uart.bus.stb, uart.bus.ack,
uart.bus.dat_r, uart.bus.dat_w, uart.bus.adr,
uart.bus.we, uart.bus.sel,
create_ilang(uart, [uart.bus.cyc, uart.bus.stb, uart.bus.ack,
uart.bus.dat_r, uart.bus.dat_w, uart.bus.adr,
uart.bus.we, uart.bus.sel,