this can occur even when fp traps are disabled in MSR, so writing
"on exceptions" is incorrect.
(due to truncation or saturation and including when the FP number was
NaN) then this is considered to be an Integer Overflow condition, and
CR0.SO, XER.SO and XER.OV are all set as normal for any GPR instructions
(due to truncation or saturation and including when the FP number was
NaN) then this is considered to be an Integer Overflow condition, and
CR0.SO, XER.SO and XER.OV are all set as normal for any GPR instructions
+that overflow. When `RT` is not written (`vex_flag = 1`), all CR0 bits
+except SO are undefined.
Special Registers altered:
Special Registers altered:
(due to truncation or saturation and including when the FP number was
NaN) then this is considered to be an Integer Overflow condition, and
CR0.SO, XER.SO and XER.OV are all set as normal for any GPR instructions
(due to truncation or saturation and including when the FP number was
NaN) then this is considered to be an Integer Overflow condition, and
CR0.SO, XER.SO and XER.OV are all set as normal for any GPR instructions
+that overflow. When `RT` is not written (`vex_flag = 1`), all CR0 bits
+except SO are undefined.
Special Registers altered:
Special Registers altered: