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Add support for CXXSim simulation
author
Cesar Strauss
<cestrauss@gmail.com>
Sun, 20 Dec 2020 14:18:34 +0000
(11:18 -0300)
committer
Cesar Strauss
<cestrauss@gmail.com>
Sun, 20 Dec 2020 14:18:34 +0000
(11:18 -0300)
src/soc/bus/test/test_sram_wishbone.py
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diff --git
a/src/soc/bus/test/test_sram_wishbone.py
b/src/soc/bus/test/test_sram_wishbone.py
index d1a6d63ae795889a566c25b1e1ad4a15a41b66d9..05ecc202624cd63fa3de5375d6d55836ece04a3b 100644
(file)
--- a/
src/soc/bus/test/test_sram_wishbone.py
+++ b/
src/soc/bus/test/test_sram_wishbone.py
@@
-5,6
+5,10
@@
Bugs:
from nmigen_soc.wishbone.sram import SRAM
from nmigen import Memory, Signal, Module
from nmigen_soc.wishbone.sram import SRAM
from nmigen import Memory, Signal, Module
+# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
+# Also, check out the cxxsim nmigen branch, and latest yosys from git
+from nmutil.sim_tmp_alternative import Simulator, Settle
+
memory = Memory(width=64, depth=16)
sram = SRAM(memory=memory, granularity=16)
memory = Memory(width=64, depth=16)
sram = SRAM(memory=memory, granularity=16)
@@
-19,7
+23,6
@@
sram = SRAM(memory=memory, granularity=16)
# sram.bus.ack
# setup simulation
# sram.bus.ack
# setup simulation
-from nmigen.back.pysim import Simulator, Delay, Settle
m = Module()
m.submodules.sram = sram
sim = Simulator(m)
m = Module()
m.submodules.sram = sram
sim = Simulator(m)