from power_enums import (Function, InternalOp, In1Sel, In2Sel, In3Sel,
OutSel, RC, LdstLen, CryIn, single_bit_flags,
get_signal_name, get_csv)
from power_enums import (Function, InternalOp, In1Sel, In2Sel, In3Sel,
OutSel, RC, LdstLen, CryIn, single_bit_flags,
get_signal_name, get_csv)
- # m.submodules.dut = dut = PowerDecoder(32, opcodes, bitsel=bitsel,
- # opint=opint, suffix=suffix)
- m.submodules.dut = dut = pdecode
+ m.submodules.dut = dut = create_pdecode()
comb += [dut.opcode_in.eq(opcode),
function_unit.eq(dut.op.function_unit),
in1_sel.eq(dut.op.in1_sel),
comb += [dut.opcode_in.eq(opcode),
function_unit.eq(dut.op.function_unit),
in1_sel.eq(dut.op.in1_sel),
+ else:
+ # OR 0, 0, 0 ; 0x60000000 is decoded as a NOP
+ # If we're testing the OR instruction, make sure
+ # that the instruction is not 0x60000000
+ if int(op, 0) == 24:
+ yield opcode[24:25].eq(0b11)
+
yield Delay(1e-6)
signals = [(function_unit, Function, 'unit'),
(internal_op, InternalOp, 'internal op'),
yield Delay(1e-6)
signals = [(function_unit, Function, 'unit'),
(internal_op, InternalOp, 'internal op'),
vl = rtlil.convert(pdecode, ports=pdecode.ports())
with open("decoder.il", "w") as f:
f.write(vl)
vl = rtlil.convert(pdecode, ports=pdecode.ports())
with open("decoder.il", "w") as f:
f.write(vl)