:attribute in2: the third input
:attribute sum: the sum output
:attribute carry: the carry output
:attribute in2: the third input
:attribute sum: the sum output
:attribute carry: the carry output
+
+ Rather than do individual full adders (and have an array of them,
+ which would be very slow to simulate), this module can specify the
+ bit width of the inputs and outputs: in effect it performs multiple
+ Full 3-2 Add operations "in parallel".
- al = []
- bl = []
- ol = []
- ea = []
- eb = []
- eo = []
+ al, bl, ol, ea, eb, eo = [],[],[],[],[],[]
+
nat, nbt, nla, nlb = [], [], [], []
for i in range(len(parts)):
# determine sign of each incoming number *in this partition*
nat, nbt, nla, nlb = [], [], [], []
for i in range(len(parts)):
# determine sign of each incoming number *in this partition*
- be = parts[i] & self.a[(i + 1) * bit_wid - 1] \ # MSB
- & self.a_signed[i * byte_width] # a op is signed?
- ae = parts[i] & self.b[(i + 1) * bit_wid - 1] \ # MSB
- & self.b_signed[i * byte_width] # b op is signed?
+ be = (parts[i] & self.a[(i + 1) * bit_wid - 1] # MSB
+ & self.a_signed[i * byte_width]) # a op is signed?
+ ae = (parts[i] & self.b[(i + 1) * bit_wid - 1] # MSB
+ & self.b_signed[i * byte_width]) # b op is signed?
a_enabled = Signal(name="a_en_%d" % i, reset_less=True)
b_enabled = Signal(name="b_en_%d" % i, reset_less=True)
m.d.comb += a_enabled.eq(ae)
a_enabled = Signal(name="a_en_%d" % i, reset_less=True)
b_enabled = Signal(name="b_en_%d" % i, reset_less=True)
m.d.comb += a_enabled.eq(ae)