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use convenience vars
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 15 Sep 2020 15:43:30 +0000
(16:43 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Tue, 15 Sep 2020 15:43:30 +0000
(16:43 +0100)
src/soc/fu/mmu/fsm.py
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diff --git
a/src/soc/fu/mmu/fsm.py
b/src/soc/fu/mmu/fsm.py
index 363948c7c15f1b8abba2707c54fd96c1a2274ad1..e991570750152e6e33266a19f4054d1f74ea94f9 100644
(file)
--- a/
src/soc/fu/mmu/fsm.py
+++ b/
src/soc/fu/mmu/fsm.py
@@
-45,6
+45,8
@@
class FSMMMUStage(ControlBase):
m.submodules.mmu = mmu = self.mmu
m.d.comb += dcache.m_in.eq(mmu.d_out)
m.d.comb += mmu.d_in.eq(dcache.m_out)
m.submodules.mmu = mmu = self.mmu
m.d.comb += dcache.m_in.eq(mmu.d_out)
m.d.comb += mmu.d_in.eq(dcache.m_out)
+ m_in, m_out = mmu.m_in, mmu.m_out
+ d_in, d_out = dcache.d_in, dcache.d_out
data_i, data_o = self.p.data_i, self.n.data_o
a_i, b_i = data_i.ra, data_i.rb
data_i, data_o = self.p.data_i, self.n.data_o
a_i, b_i = data_i.ra, data_i.rb
@@
-83,29
+85,29
@@
class FSMMMUStage(ControlBase):
# pass it over to the MMU instead
with m.Else():
# kick the MMU and wait for it to complete
# pass it over to the MMU instead
with m.Else():
# kick the MMU and wait for it to complete
- comb += m
mu.m
_in.valid.eq(1) # start
- comb += m
mu.m
_in.mtspr.eq(1) # mtspr mode
- comb += m
mu.m
_in.sprn.eq(spr) # which SPR
- comb += m
mu.m
_in.rs.eq(a_i) # incoming operand (RS)
- comb += done.eq(m
mu.m
_out.done) # zzzz
+ comb += m_in.valid.eq(1) # start
+ comb += m_in.mtspr.eq(1) # mtspr mode
+ comb += m_in.sprn.eq(spr) # which SPR
+ comb += m_in.rs.eq(a_i) # incoming operand (RS)
+ comb += done.eq(m_out.done) # zzzz
with m.Case(MicrOp.OP_DCBZ):
# activate dcbz mode (spec: v3.0B p850)
with m.Case(MicrOp.OP_DCBZ):
# activate dcbz mode (spec: v3.0B p850)
- comb += d
cache.d
_in.valid.eq(1) # start
- comb += d
cache.d
_in.dcbz.eq(1) # dcbz mode
- comb += d
cache.d
_in.addr.eq(a_i + b_i) # addr is (RA|0) + RB
- comb += done.eq(d
cache.d
_out.done) # zzzz
+ comb += d_in.valid.eq(1) # start
+ comb += d_in.dcbz.eq(1) # dcbz mode
+ comb += d_in.addr.eq(a_i + b_i) # addr is (RA|0) + RB
+ comb += done.eq(d_out.done) # zzzz
with m.Case(MicrOp.OP_TLBIE):
# pass TLBIE request to MMU (spec: v3.0B p1034)
# note that the spr is *not* an actual spr number, it's
# just that those bits happen to match with field bits
# RIC, PRS, R
with m.Case(MicrOp.OP_TLBIE):
# pass TLBIE request to MMU (spec: v3.0B p1034)
# note that the spr is *not* an actual spr number, it's
# just that those bits happen to match with field bits
# RIC, PRS, R
- comb += m
mu.m
_in.valid.eq(1) # start
- comb += m
mu.m
_in.tlbie.eq(1) # mtspr mode
- comb += m
mu.m
_in.sprn.eq(spr) # use sprn to send insn bits
- comb += m
mu.m
_in.addr.eq(b_i) # incoming operand (RB)
- comb += done.eq(m
mu.m
_out.done) # zzzz
+ comb += m_in.valid.eq(1) # start
+ comb += m_in.tlbie.eq(1) # mtspr mode
+ comb += m_in.sprn.eq(spr) # use sprn to send insn bits
+ comb += m_in.addr.eq(b_i) # incoming operand (RB)
+ comb += done.eq(m_out.done) # zzzz
with m.If(self.n.ready_i & self.n.valid_o):
m.d.sync += busy.eq(0)
with m.If(self.n.ready_i & self.n.valid_o):
m.d.sync += busy.eq(0)