+directly into Register Hazard Management
+
+As long as the SVSHAPE SPRs
+are not written to directly, Hardware may treat REMAP as 100%
+Deterministic: all REMAP Management instructions take static
+operands with the exception of Indexed Mode, and even then
+Architectural State is permitted to assume that the Indices
+are cacheable from the point at which the `svindex` instruction
+is executed.