- pll = Instance("pll", i_ref=self.clk_24_i,
- i_a0=self.clk_sel_i[0],
- i_a1=self.clk_sel_i[1],
- o_out_v=self.clk_pll_o,
- o_div_out_test=self.pll_test_o,
- o_vco_test_ana=self.pll_vco_o,
+ clk_24_i = Signal(reset_less=True) # external incoming
+ clk_sel_i = Signal(2, reset_less=True) # PLL selection
+ clk_pll_o = Signal(reset_less=True) # output clock
+ pll_test_o = Signal(reset_less=True) # test out
+ pll_vco_o = Signal(reset_less=True) # analog
+ pll = Instance("pll", i_ref=clk_24_i,
+ i_a0=clk_sel_i[0],
+ i_a1=clk_sel_i[1],
+ o_out_v=clk_pll_o,
+ o_div_out_test=pll_test_o,
+ o_vco_test_ana=pll_vco_o,