+""" Computation Unit (aka "ALU Manager").
+
+ This module runs a "revolving door" set of three latches, based on
+ * Issue
+ * Go_Read
+ * Go_Write
+ where one of them cannot be set on any given cycle.
+ (Note however that opc_l has been inverted (and qn used), due to SRLatch
+ default reset state being "0" rather than "1")
+
+ * When issue is first raised, a busy signal is sent out.
+ The src1 and src2 registers and the operand can be latched in
+ at this point
+
+ * Read request is set, which is ackowledged through the Scoreboard
+ to the priority picker, which generates (one and only one) Go_Read
+ at a time. One of those will (eventually) be this Computation Unit.
+
+ * Once Go_Read is set, the src1/src2/operand latch door shuts (locking
+ src1/src2/operand in place), and the ALU is told to proceed.
+
+ * As this is currently a "demo" unit, a countdown timer is activated
+ to simulate an ALU "pipeline", which activates "write request release",
+ and the ALU's output is captured into a temporary register.
+
+ * Write request release will go through a similar process as Read request,
+ resulting (eventually) in Go_Write being asserted.
+
+ * When Go_Write is asserted, two things happen: (1) the data in the temp
+ register is placed combinatorially onto the output, and (2) the
+ req_l latch is cleared, busy is dropped, and the Comp Unit is back
+ through its revolving door to do another task.
+"""