- def __init__(self, i_width=1, stage_ctl=False):
+ def __init__(self, i_width=1, stage_ctl=False, maskwid=0):
self.valid_i = Signal(i_width, name="p_valid_i") # prev >>in self
self._ready_o = Signal(name="p_ready_o") # prev <<out self
self.data_i = None # XXX MUST BE ADDED BY USER
self.valid_i = Signal(i_width, name="p_valid_i") # prev >>in self
self._ready_o = Signal(name="p_ready_o") # prev <<out self
self.data_i = None # XXX MUST BE ADDED BY USER
valid_i = prev.valid_i if direct else prev.valid_i_test
res = [self.valid_i.eq(valid_i),
prev.ready_o.eq(self.ready_o)]
valid_i = prev.valid_i if direct else prev.valid_i_test
res = [self.valid_i.eq(valid_i),
prev.ready_o.eq(self.ready_o)]
self.ready_o.eq(i.ready_o),
self.valid_i.eq(i.valid_i)]
self.ready_o.eq(i.ready_o),
self.valid_i.eq(i.valid_i)]
if hasattr(self.data_i, "ports"):
yield from self.data_i.ports()
elif isinstance(self.data_i, Sequence):
if hasattr(self.data_i, "ports"):
yield from self.data_i.ports()
elif isinstance(self.data_i, Sequence):