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add chip conversion from ghdl to verilog
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 17 Apr 2021 10:52:48 +0000
(11:52 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Sat, 17 Apr 2021 10:52:48 +0000
(11:52 +0100)
ls180/post_pnr/Makefile
patch
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diff --git
a/ls180/post_pnr/Makefile
b/ls180/post_pnr/Makefile
index c0a63c8bb687ce941f3f85bb266cc2de7ef1efbd..feeea4fdd7aa71b835a0866259c63858d81b134b 100644
(file)
--- a/
ls180/post_pnr/Makefile
+++ b/
ls180/post_pnr/Makefile
@@
-1,4
+1,4
@@
-.PHONY: all c
orona
prepare cocotb gitupdate
+.PHONY: all c
hip
prepare cocotb gitupdate
all: prepare cocotb
all: prepare cocotb
@@
-16,8
+16,12
@@
cocotb:
(cd cocotb && ./run_ghdl.sh)
# builds just for fun (double-check) ghdl works
(cd cocotb && ./run_ghdl.sh)
# builds just for fun (double-check) ghdl works
-c
orona
:
+c
hip
:
./vhd2obj.py
./vhd2obj.py
- (cd obj && ghdl -e -g --std=08 c
orona
)
- (cd obj && ghdl -r -g --std=08 c
orona
)
+ (cd obj && ghdl -e -g --std=08 c
hip
)
+ (cd obj && ghdl -r -g --std=08 c
hip
)
+# imports all ghdl "stuff" and outputs verilog
+chip_v: chip
+ (cd obj && yosys -m ghdl -p 'ghdl --std=08 chip' \
+ -p 'proc' -p 'write_verilog chip.v')